Recently, as high integration and high performance of LSIs have progressed, miniaturization of MISFET (Metal/Insulator/Semiconductor Field Effect Transistor) is advanced and its gate length is scaled, so that a problem of the short-channel effect which lowers a threshold voltage Vth has become significant. The short-channel effect is caused by the fact that a spread of a depletion layer in source and drain portions of the MISFET influences a channel portion according to miniaturization of the channel length. Increasing impurity concentration in the channel portion to suppress the spread of the depletion layer in the source and drain portions is one of methods for suppressing the influence. But if the impurity concentration in the channel portion is increased, degradation of drive current becomes problematic depending on carrier mobility resulting from increase of impurity scattering. Further, if the impurity concentration is increased, parasitic capacitances among the substrate, the source, and the drain are increased and thus fast operation of the MISFET is hampered.
Further, conventionally, the threshold voltage Vth of the MISFET is controlled by the impurity concentration of a channel region. Impurity concentration control of channel is relatively well performed up to an LSI of the design rule of about 100 nm node by using an ion implantation technique and a short heat treatment technique.
As to an MISFET of the design rule of 100 nm node or subsequent thereto, however, since an absolute number of impurities contributing to the threshold voltage Vth of MISFET per one is reduced along with the channel length shortened by the method of controlling the threshold voltage Vth by an impurity amount in the channel, variation of the threshold voltage Vth caused by statistical fluctuation cannot be ignored (for example, see Non-Patent Document 1). Therefore, it has been longed to make it possible to control the threshold value Vth of the MISFET according to a work function of a gate electrode as well by the impurity concentration control of a channel portion and another method as a miniaturized device-matching process.
In order to solve such a problem, in recent years, SOI structure has attracted attentions. In this structure, complete device isolation is made by an insulating film (for example, silicon oxide film), and so soft error and latch up are suppressed, so that high reliability is gained even in a highly-integrated LSI, and moreover, since junction capacitance of a diffusion layer is reduced, charge and discharge resulting from switching are reduced and so it is advantageous for achieving high speed and low power consumption.
The SOI type MISFETs are roughly classified to two operation modes. One of these is a Full Depletion SOI in which a depletion layer induced in a body region beneath a gate electrode reaches a bottom surface of the body region, namely, an interfacial surface between the body region and an buried oxide film, and the other is a Partial Depletion SOI in which the depletion layer does not reach the bottom surface of the body region and there remains a neutral region.
In the full depletion type SOI-MISFET, since the thickness of the depletion layer just below the gate is limited by the buried oxide film, a depletion charge amount is considerably reduced as compared to the partial depletion SOI-MISFET, and instead, mobile charges contributing to a drain current are increased. As a result, there is an advantage that a steep sub-threshold characteristic (S characteristic) can be obtained.
In other words, when a steep S characteristic is obtained, the threshold voltage Vth can be lowered while suppressing off-leakage current. As a result, a drain current is secured even at a low operating voltage, so that it becomes possible to manufacture a MISFET with extremely low power consumption such as a MISFET operating at 1V or lower (the threshold voltage Vth is also 0.3 V or lower).
Further, generally, in a case of a MISFET manufactured on a substrate, there is the abovementioned problem of short-channel effect. Meanwhile, in a case of the full depletion type SOI-MISFET, since the substrate and the device are isolated from each other by an oxide film and the depletion layer will not spread, a substrate concentration can be lowered in the full depletion type SOI-MISFET. Therefore, since lowering of carrier mobility along with increase of impurity scattering is suppressed, high drive current can be achieved. Further, as compared to the method of controlling the threshold voltage Vth by impurity concentration, variation of the threshold voltage Vth caused by statistical fluctuation of the number of impurities with respect to one MISFET can be reduced.
On the other hand, a double-gate MISFET structure has been known as another conventional technique relating to the SOI-MISFET, which has been proposed in Patent Document 1, for example. In the above SOI-MISFET, after a source diffusion layer and a drain diffusion layer are formed in an SOI layer according to self-alignment with a dummy gate electrode, formation of a reverse pattern groove of the dummy gate electrode and formation of a buried gate according to ion implantation of impurities from the groove to a supporting substrate are performed sequentially, thereafter, a metal film such as W (tungsten) is selectively buried in the groove region, thereby an upper gate electrode is made. Realization of the double-gate structure is potential means as means for improving SOI-MISFET performance, but in the double-gate MISFET structure based on presently well-known means, it is extremely difficult to form a high-concentration diffusion layer or the like in a buried manner in the supporting substrate without adversely affecting the SOI layer, and thus the double-gate MISFET structure has not reached practical use yet. When difficulty in manufacture is ignored and an essential concept of the double-gate MISFET structure is taken into account, it is a premise that a buried gate and an upper gate are aligned accurately, and it is necessarily required to arrange the buried gate for each individual device. Such a concept of sharing the role of the buried gate electrode by a plurality of MISFETs does not basically exist. Alignment error of the buried gate is fatal in an ultrafine SOI-MISFET and directly leads to variation of parasitic capacitance and variation of drive current. Therefore, even if the parasitic capacitor is effectively utilized for stabilization of a dynamic operation, utilization of the parasitic capacitor for stabilization is also irrealizable unless capacitance variation is suppressed essentially. Further, since the threshold voltage of the double-gate structure SOI-MISFET is determined only by a work function of each material for the upper gate and the buried gate except for a component of SOI layer film thickness, it is substantially impossible to set a threshold voltage value for each desired MISFET. It is a premise that a connection between the buried gate electrode and the upper gate electrode is made outside an MISFET active region, namely, in a device isolation region, and consistency with a consideration of peripheral device layout is essential.
Herein, in the above full depletion type SOI-MISFET manufactured by using an SOI substrate with a buried insulating film having a thickness of 50 nm or less, more preferably 10 nm or less, and a thin single crystal semiconductor thin film having a thickness of 20 nm or less, by applying a gate potential to a well diffusion layer just below the SOI-MISFET, a conduction state of the SOI-MISFET is further accelerated due to a high-potential application of a well potential via the thin buried insulating film, which causes significant increase of drive current, namely, achieves high current. When the gate potential is applied as a low potential, the well potential is lowered in a following manner, so that a non-conduction state can be achieved faster. That is, a characteristic of further increasing drive current under the same condition of leakage current can be realized in the above operation mode, so that it becomes possible to perform switching between conduction and non-conduction at a higher speed. Isolation for insulation on sidewalls of a well diffusion layer contributes to reduction of a parasitic capacitance, namely, reduction of a delay time constant of an application signal. Further, the thinner the buried insulating film is, the more effective for improvement of an increase effect of the drive current, and ideally, a film thickness condition equivalent to that of the gate insulating film of the SOI-MISFET is preferable. As described above, by applying the thin buried insulating film to the SOI-MISFET, a characteristic of essential performance improvement of the SOI-MISFET according to the double-gate structure can be utilized. Further, since the well diffusion layer just below the SOI-MISFET is formed in a self-aligned manner under the gate electrode, the problems of drive current variation and parasitic capacitance variation caused by an alignment error of the buried gate electrode, which are problematic in a conventional double-gate MISFET structure, can be essentially removed.
As described above, the SOI-type MISFET has such an excellent feature as low power consumption and high speed.
Patent Document 1: Japanese Patent Application Laid-Open Publication No. 2000-208770
Non-Patent Document 1: T. Mizuno et al. “Performance Fluctuations of 0.10 μm MOSFETs—Limitation of 0.10μ ULSIs”, Symp. On VLSI Technology 1994
Non-Patent Document 2: T. Yamada et al. “An Embedded DRAM Technology on SOI/Bulk Hybrid Substrate Formed with SEG Process for High-End SOC Application” Symp. On VLSI Technology 2002